Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with MTJ technology, is a major emerging technology that is highly competitive with existing semiconductor memories such as SRAM, DRAM, and Flash. Similarly, spin-transfer (spin torque) magnetization switching described by C. Slonczewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), has recently stimulated considerable interest due to its potential application for spintronic devices such as STT-RAM on a gigabit scale.
As shown in FIG. 1, one embodiment of a memory cell in a STT-RAM 1 includes a gate 5 formed above a p-type semiconductor substrate 2, a source 3, drain 4, word line (WL) 7 above the gate, and a source line 9. There is also a bottom electrode (BE) 10 formed above the source line 9 and word line 7, and a MTJ cell 11 between the BE and bit line (BL) 12. There is a Cu stud 6 connecting the source 3 to BL 12, and a via 13 and Cu stud 8 to connect BE 10 to drain 4. Thus, the transistor source 3 and drain 4 are connected to the MTJ 11 so that DC current may flow across the MTJ.
Both field-MRAM and STT-RAM have a MTJ element based on a tunneling magneto-resistance (TMR) effect wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. The MTJ element is typically formed between a bottom electrode such as a first conductive line and a top electrode which is a second conductive line at locations where the top electrode crosses over the bottom electrode. A MTJ stack of layers may have a bottom spin valve configuration in which a seed layer, an anti-ferromagnetic (AFM) pinning layer, a ferromagnetic “pinned” layer, a thin tunnel barrier layer, a ferromagnetic “free” layer, and a capping layer are sequentially formed on a bottom electrode. The AFM layer holds the magnetic moment of the pinned layer in a fixed direction. The pinned layer has a magnetic moment that is fixed in the “x” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “x” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“0” memory state) and a higher resistance is noted when they are in an anti-parallel state or “1” memory state.
In a read operation, the information stored in a field-MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the field-MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. One line (bit line) provides the field parallel to the easy axis of the bit while another line (digit line) provides the perpendicular (hard axis) component of the field. The intersection of the lines generates a peak field that is engineered to be just over the switching threshold of the MTJ.
A high performance MRAM MTJ element is characterized by a high tunneling magnetoresistive (TMR) ratio which is dR/R where R is the minimum resistance of the MTJ element and dR is the change in resistance observed by changing the magnetic state of the free layer. A high TMR ratio and resistance uniformity (Rp_cov), and a low switching field (Hc) and low magnetostriction (λS) value are desirable for conventional MRAM applications. For Spin-RAM (STT-RAM), a high λS and high Hc leads to high anisotropy for greater thermal stability. This result is accomplished by (a) well controlled magnetization and switching of the free layer, (b) well controlled magnetization of a pinned layer that has a large exchange field and high thermal stability and, (c) integrity of the tunnel barrier layer. In order to achieve good barrier properties such as a specific junction resistance x area (RA) value and a high breakdown voltage (Vb), it is necessary to have a uniform tunnel barrier layer which is free of pinholes that is promoted by a smooth and densely packed growth in the AFM and pinned layers. RA should be relatively small (<10000 ohm-μm2) for MTJs that have an area defined by an easy axis and hard axis dimensions of less than 1 micron.
As the size of MRAM cells decreases, the use of external magnetic fields generated by current carrying lines to switch the magnetic moment direction becomes problematic. One of the keys to manufacturability of ultra-high density MRAMs is to provide a robust magnetic switching margin by eliminating the half-select disturb issue. For this reason, a new type of device called a spin transfer (spin torque) device was developed. Compared with conventional MRAM, spin-transfer torque or STT-RAM has an advantage in avoiding the half select problem and writing disturbance between adjacent cells. The spin-transfer effect arises from the spin dependent electron transport properties of ferromagnetic-spacer-ferromagnetic multilayers. When a spin-polarized current transverses a magnetic multilayer in a CPP configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. As a result, spin-polarized current can switch the magnetization direction of the ferromagnetic layer if the current density is sufficiently high, and if the dimensions of the multilayer are small. The difference between a STT-RAM and a conventional MRAM is only in the write operation mechanism. The read mechanism is the same.
For STT-RAM to be viable in the 90 nm technology node and beyond, the ultra-small MTJs (also referred to as nanopillars or nanomagnets herein) must exhibit a TMR ratio that is much higher than in a conventional MRAM-MTJ which uses AlOx as the tunnel barrier and a NiFe free layer. Furthermore, the critical current density (Jc) must be lower than about 106 A/cm2 to be driven by a CMOS transistor that can typically deliver 100 μA per 100 nm gate width. A critical current for spin transfer switching (Ic), which is defined as [(Ic++Ic−)/2], for the present 180 nm node sub-micron MTJ having a top-down area of about 0.2×0.4 micron, is generally a few milliamperes. The critical current density (Jc), for example (Ic/A), is on the order of several 107 A/cm2. This high current density, which is required to induce the spin-transfer effect, could destroy a thin tunnel barrier made of AlOx, MgOx, or the like. Thus, for high density devices such as STT-RAM on a gigabit scale, it is desirable to decrease Ic (and its Jc) by approximately an order of magnitude so as to avoid an electrical breakdown of the MTJ device and to be compatible with the underlying CMOS transistor that is used to provide switching current and to select a memory cell.
Once a certain MTJ cell has been written to, the circuits must be able to detect whether the MTJ is in a high or low resistance state which is called the “read” process. Uniformity of the TMR ratio and the absolute resistance of the MTJ cell are critical in field-MRAM (and STT-RAM) architecture since the absolute value of MTJ resistance is compared with a reference cell in a fixed resistance state during read mode. Needless to say, the read process introduces some statistical difficulties associated with the variation of resistances of MTJ cells within an array. If the active device resistances in a block of memory show a large resistance variation (i.e. high Rp_cov, Rap_cov), a signal error can occur when they are compared with a reference cell. In order to have a good read operation margin, TMR ratio/Rp_cov (or Rap_cov) should be greater than 12, preferably >15, and most preferably >20 where Rp is the MTJ resistance for free layer magnetization aligned parallel to pinned layer magnetization (which is fixed) and Rap is the resistance of free layer magnetization aligned anti-parallel to the pinned layer magnetization.
The intrinsic critical current density (Jc) as given by Slonczewski of IBM is shown in equation (1) below.Jc=2eαMstF(Ha+Hk+2πMs)/η  (1)where e is the electron charge, α is a Gilbert damping constant, tF is the thickness of the free layer, h is the reduced Plank's constant, η is the spin-transfer efficiency which is related to the spin polarization (P), Ha is the external applied field, Hk is the uniaxial anisotropy field, and 2π Ms is the demagnetization field of the free layer. Two publications by C. Slonczewski that relate to STT-RAM are entitled “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), and “Current, torques, and polarization factors in magnetic tunnel junctions”, Physical Review B 71, 024411(2005). In a MTJ structure (F/I/F) where F is a ferromagnetic layer and I is an insulator, when the spin relaxation distance is much larger than the ferromagnetic film thickness, the spin continuity holds true, i.e., the sum of interfacial torques from both left and right sides equals the net inflow of spin current. As the magnetization is fixed on one side, the other side magnetization will experience an in-plane torque of T=−(PLJ0/2e)sin(θ) where e is the electron charge, PL is tunneling polarization parameter, J0 is electric current density, and θ is the angle between the magnetizations on the two sides of the tunnel barrier (insulator).
Normally, the demagnetizing field, 2πMs (several thousand Oe term) is much larger than the uniaxial anisotropy field Hk and external applied field (approximately 100 Oe) Ha term, hence the effect of Hk and Ha on Jc are small. In equation (2), V equals Ms(tFA) and is the magnetic volume which is related to the thermal stability function term KuV/kbT where Ku is the magnetic anisotropy energy and kb is the Boltzmann constant.Jc∝αMsV/η  (2)
Another publication relating to a STT-RAM (Spin-RAM) structure is by M. Hosomi et al. in “A novel non-volatile memory with spin torque transfer magnetization switching: Spin-RAM”, 2005 IEDM, paper 19-1, and describes a 4 Kbit Spin RAM having CoFeB pinned and free layers, and a RF-sputtered MgO tunnel barrier that was annealed under 350° C. and 10000 Oe conditions. The MTJ size is 100 nm×150 nm in an oval shape. The tunnel barrier is made of crystallized (001) MgO with a thickness controlled to <10 Angstroms for a proper RA of around 20 ohm-um2. Intrinsic dR/R of the MTJ stack is 160% although dR/R for the 100 nm×150 nm bit during read operation (with 0.1 V bias) is about 90% to 100%. Using a 10 ns pulse width, the critical current density, Jc, for spin transfer magnetization switching is around 2.5×106 A/cm2. Write voltage distribution on a 4 Kbit circuit for high resistance state to low resistance (P to AP) and low resistance state to high resistance state (AP to P) has shown good write margin. Resistance distribution for the low resistance state (Rp) and high resistance state (Rap) has a sigma (Rp_cov) of about 4%. Thus, for a read operation, TMR (with 0.1 V bias)/Rp_cov is >20.
T. Kawahara et al. in “2 Mb Spin-transfer torque RAM with bit-by-bit bi-directional current write and parallelizing-direction current read”, 2007 IEEE International Solid State Circuits Conference, describe a prototype RAM with a CoFe(B)/RF-sputtered MgO/CoFe—NiFe MTJ. With an MgO tunnel barrier thickness of 10 Angstroms, the RA is around 20 ohm-μm2. A TMR of ˜100% is achieved when the annealing temperature is 350° C. Switching voltage for a 100 nm×50 nm oval MTJ using a 100 ns pulse is around 0.7 V and Jc is 2 to 3×106 A/cm2. The switching was operated in a thermally assisted regime (100 ns write pulse).
In S. Oh et al. “Excellent scalability and switching characteristics in spin-transfer torque MRAM”, IEDM 2006, conventional lithography and dry etching techniques are used to make sub-50 nm MTJ cell sizes and thereby achieve Gb density. Low switching current density (Jc) of 1.63×106 A/cm2 with 10 ns pulse was realized through optimizing magnetic materials in a CoFeB/MgO/CoFeB MTJ structure.
S. Honda et al. in “Tunneling giant magnetoresistance in heterogeneous Fe—SiO2 granular films”, Phys. Rev. B, V56, p 14566 (1997), and in “Tunneling magnetoresistance in ultrathin Co—SiO2 granular films”, JAP, V93, p 7936 (2003), examined the thickness dependencies of magnetic and TMR properties in Fe—SiO2 and Co—SiO2 films. Because of the Fe—O or Fe(Si)—O shells surrounding Fe granules, the isolated Fe(FeSi) granule diameter for the sputtered Fe(40 at. %)-SiO2 film is distributed between 10 and 25 Angstroms. In Co—SiO2 granular films, the isolated Co granule diameter is on the same order as its thickness (i.e. columnar growth) because the formation of non-magnetic shells surrounding Co granules is fairly suppressed.
In U.S. Pat. No. 7,488,609, a first MgO tunnel barrier layer is formed over a ferromagnetic layer in a TMR device by DC magnetron sputtering from an Mg target in an oxygen environment. Then a second MgO layer is formed on the first MgO layer by sputter depositing a MgO layer in a non-oxygen environment.
The references above clearly indicate that spin-transfer-torque writing is a viable candidate for low power, high density non-volatile RAM. The prior art MTJ structures for STT-RAM typically use a CoFeB pinned layer, a RF sputter deposited MgO layer, and a CoFeB or CoFe/NiFe free layer. However, a lower switching current density (Jc) and a lower RA than obtained from RF sputtered Mg0 films are desired for optimum performance in advanced products including 64 Mb STT-RAM products. Furthermore, a low Jc value must be achieved simultaneously with acceptable values for read voltage (VR), write voltage (VW), Hc for storage, and thermal stability (Eb).
In previous disclosures from MagIC Technologies, natural oxidation (NOX) methods are described for forming a Mg0 tunnel barrier layer. U.S. Pat. No. 7,479,394 discloses a method involving the oxidation of a first Mg layer with a radical oxidation (ROX) step and then deposition of a second Mg layer which is subsequently oxidized by a NOX method. A third Mg layer may be formed as the top layer in the stack. In U.S. Patent Application 2009/0108383, a first Mg layer is oxidized by a NOX method and then a second Mg layer is formed on the MgO layer. U.S. Pat. No. 7,480,173 includes a MgO tunnel barrier layer with a thickness between 0.5 and 2 nm in a STT-MRAM.
In. U.S. Pat. No. 7,411,817, a MTJ is disclosed wherein a magnetic soft free layer is pinned by an AFM 1 layer (e.g. IrMn) which has a lower blocking temperature than the AFM 2 layer (e.g. MnPt) used to pin the pinned layer. During the write process, heating is induced in the MTJ to a temperature higher than the blocking temperature of AFM 1 but still lower than that of AFM 2 thereby allowing the free layer in the absence of AFM 1 pinning to be switched more easily.